Jon (j_b) wrote,
Jon
j_b

I hate computers.


Triggurhorse: so why you be hatin' linux?
Thoreandan: oh
Thoreandan: see
Thoreandan: you can understand this one
Thoreandan: remember dos?
Thoreandan: remember x86 IN and OUT
Triggurhorse: yeah.
Triggurhorse: vaguely.
Thoreandan: doing IN from 0x03f8
Thoreandan: reading serial port
Thoreandan: making things go 'bleep' on paralell port etc
Thoreandan: well
Thoreandan: see
Triggurhorse: oh yeah.
Thoreandan: Since Linux is not a single unified "Cathedral" project like BSD, and is more like a "Bazaar" project, that means it's sprayed like so much projectile diarrhea all over the 'net
Thoreandan: and when you're working with something you might be lucky if the sourcecode to the kernel has a txt file on it
Triggurhorse: lovely analogy. :-)
Thoreandan: or maybe it won't, and you'll have to go find the homepage for the subsection you're interested in, find the IRC channel devoted to it, and from the topic of that IRC channel find one guys homepage who has the patch file you need there for download (which is NOT in the sourceforge project *OR* checked into the kernel rev that it applies to) and you apply it with "patch -p1 < beware_of_leopard"
Thoreandan: anyway
Thoreandan: so I am cleaning up my system
Thoreandan: so I am rolling a new fresh pretty filesystem on an alternate disk
Triggurhorse: nice.
Triggurhorse: Me, I'm about to go openbsd.
Thoreandan: so I made the /usr partition [read only], set up /var /var/mail etc etc
Thoreandan: and it came time to do dev
Thoreandan: so
Thoreandan: I look at the MAKEDEV script that comes with Debian Woody
Thoreandan: it has an invocation [according to the HA HA HA HA man page HAH AH AHA HA ] that cretes basic files, MAKEDEV std
Thoreandan: so far so good, that makes /dev/zero, /dev/null , etc
Thoreandan: then I run MAKEDEV update which according to the [hah] manpage says it will probe the kernel for what major/minor's are defined in the kernel but don't have device nodes, and make those devices
Thoreandan: well, it instead makes every conceivable device it knows about including /dev/amigamouse
Thoreandan: let me TELL ya how much I like /dev/amigamouse
Thoreandan: so
Thoreandan: I notice that if I try "cat amigamouse" it errors "No such device"
Thoreandan: bright idea occurs
Thoreandan: write a script, try to cat each device in dev, log the ones that error
Thoreandan: remove those
Thoreandan: ah! but some devices like /dev/random and /dev/zero spew infinitely
Thoreandan: I am too smart
Thoreandan: I do cat -v /dev/$foo | head --bytes=30
Thoreandan: I run script
Thoreandan: script starts...
Thoreandan: script makes it down to /dev/port
Thoreandan: /dev/port's convenient, you know, it emulates a 64K flat readable file, but every read or write on it goes directly to the CPU's I/O PORTS!!!
Triggurhorse: eek
Thoreandan: so it was essentially like 10 FOR X=1 TO STD_BUF_SZ: PRINT CHR$(PEEK(X));:NEXT X
Thoreandan: machine went "D'aahhhhhhhhhhrrrrrrrrrrrrrrr", locked up hard, no ping no nothin'
Thoreandan: machine is 11 miles away in south denver in an empty office
Thoreandan: I was sad

[edit]
Ralf Brown is cool. inter61d.zip reveals PORTS.A, which explains what got twiddled:

PORT 0000-001F - DMA 1 - FIRST DIRECT MEMORY ACCESS CONTROLLER (8237)
SeeAlso: PORT 0080h-008Fh"DMA",PORT 00C0h-00DFh

0000 R- DMA channel 0 current address byte 0, then byte 1
0000 -W DMA channel 0 base address byte 0, then byte 1
0001 RW DMA channel 0 word count byte 0, then byte 1
0002 R- DMA channel 1 current address byte 0, then byte 1
0002 -W DMA channel 1 base address byte 0, then byte 1
0003 RW DMA channel 1 word count byte 0, then byte 1
0004 R- DMA channel 2 current address byte 0, then byte 1
0004 -W DMA channel 2 base address byte 0, then byte 1
0005 RW DMA channel 2 word count byte 0, then byte 1
0006 R- DMA channel 3 current address byte 0, then byte 1
0006 -W DMA channel 3 base address byte 0, then byte 1
0007 RW DMA channel 3 word count byte 0, then byte 1

0008 R- DMA channel 0-3 status register (see #P0001)
0008 -W DMA channel 0-3 command register (see #P0002)
0009 -W DMA channel 0-3 write request register (see #P0003)
000A RW DMA channel 0-3 mask register (see #P0004)
000B -W DMA channel 0-3 mode register (see #P0005)

000C -W DMA channel 0-3 clear byte pointer flip-flop register
any write clears LSB/MSB flip-flop of address and counter registers
000D R- DMA channel 0-3 temporary register
000D -W DMA channel 0-3 master clear register
any write causes reset of 8237
000E -W DMA channel 0-3 clear mask register
any write clears masks for all channels
000F rW DMA channel 0-3 write mask register (see #P0006)
Notes: the temporary register is used as holding register in memory-to-memory
DMA transfers; it holds the last transferred byte
channel 2 is used by the floppy disk controller
on the IBM PC/XT channel 0 was used for the memory refresh and
channel 3 was used by the hard disk controller
on AT and later machines with two DMA controllers, channel 4 is used
as a cascade for channels 0-3
command and request registers do not exist on a PS/2 DMA controller

Bitfields for DMA channel 0-3 status register:
Bit(s) Description (Table P0001)
7 channel 3 request active
6 channel 2 request active
5 channel 1 request active
4 channel 0 request active
3 channel terminal count on channel 3
2 channel terminal count on channel 2
1 channel terminal count on channel 1
0 channel terminal count on channel 0
SeeAlso: #P0002,#P0481

Bitfields for DMA channel 0-3 command register:
Bit(s) Description (Table P0002)
7 DACK sense active high
6 DREQ sense active high
5 =1 extended write selection
=0 late write selection
4 rotating priority instead of fixed priority
3 compressed timing (two clocks instead of four per transfer)
=1 normal timing (default)
=0 compressed timing
2 =1 enable controller
=0 enable memory-to-memory
1-0 channel number
SeeAlso: #P0001,#P0004,#P0005,#P0482

Bitfields for DMA channel 0-3 request register:
Bit(s) Description (Table P0003)
7-3 reserved (0)
2 =0 clear request bit
=1 set request bit
1-0 channel number
00 channel 0 select
01 channel 1 select
10 channel 2 select
11 channel 3 select
SeeAlso: #P0004

Bitfields for DMA channel 0-3 mask register:
Bit(s) Description (Table P0004)
7-3 reserved (0)
2 =0 clear mask bit
=1 set mask bit
1-0 channel number
00 channel 0 select
01 channel 1 select
10 channel 2 select
11 channel 3 select
SeeAlso: #P0001,#P0002,#P0003,#P0484

Bitfields for DMA channel 0-3 mode register:
Bit(s) Description (Table P0005)
7-6 transfer mode
00 demand mode
01 single mode
10 block mode
11 cascade mode
5 direction
=0 increment address after each transfer
=1 decrement address
3-2 operation
00 verify operation
01 write to memory
10 read from memory
11 reserved
1-0 channel number
00 channel 0 select
01 channel 1 select
10 channel 2 select
11 channel 3 select
SeeAlso: #P0002,#P0485

Bitfields for DMA channel 0-3 write mask register:
Bit(s) Description (Table P0006)
7-4 reserved
3 channel 3 mask bit
2 channel 2 mask bit
1 channel 1 mask bit
0 channel 0 mask bit
Note: each mask bit is automatically set when the corresponding channel
reaches terminal count or an extenal EOP sigmal is received
SeeAlso: #P0004,#P0486
----------P0010001F--------------------------
PORT 0010-001F - DMA CONTROLLER (8237) ON PS/2 MODEL 60 & 80
SeeAlso: PORT 0000h-001Fh,PORT 0080h-008Fh"DMA",PORT 00C0h-00DFh

0018 -W extended function register (see #P0007)
001A -W extended function execute register

Bitfields for DMA extended function register:
Bit(s) Description (Table P0007)
7-4 function code (see #P0008)
3 reserved (0)
2-0 channel number
000 channel 0 select
001 channel 1 select
010 channel 2 select
011 channel 3 select
100 channel 4 select
101 channel 5 select
110 channel 6 select
111 channel 7 select

(Table P0008)
Values for DMA extended function codes (data go to/from PORT 001Ah):
Value Description Parameters Results
00h current address register - CA0,CA1
02h write address - A0,A1,P
03h read address A0,A1,P -
04h write word count register C0,C1 -
05h read word count register - C0,C1
06h read status register - S
07h mode register - M
09h mask channel - -
0Ah unmask channel - -
0Dh master clear - -
Note: CA0/CA1 LSB/MSB of the current address register
A0/A1 LSB/MSB of the base address register
P DMA page address
C0/C1 LSB/MSB of the word count register
S status register value (see #P0001, #P0481)
M mode register value (see #P0005, #P0485)
first, the extended function register is written, then the extended
function register execute register is read/written if the function
being executing requires

Bitfields for DMA extended mode register:
Bit(s) Description (Table P0009)
7 reserved (0)
6 =0 8-bit transfer
=1 16-bit transfer
5-4 reserved (0)
3 transfer type
=0 read from memory
=1 write to memory
2 =0 disable memory write
=1 enable memory write
1 reserved (0)
0 address select
=0 use 0 as base address
=1 use a value from base address register


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